PHASE LOCKED LOOP INCLUDING NON-INTEGER MULTIPLE FREQUENCY REFERENCE SIGNAL

摘要

A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner tominimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop. (FIG. 1)