High resolution image processor with multiple bus architecture

摘要

A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2Kx2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.