| 摘要 |
In this semiconductor integrated circuit device, an internal power supply circuit and an external terminal are connected to each other via a switch circuit having an n channel MOS transistor and a p channel MOS transistor connected in series. While a control signal is input to a gate of the n channel MOS transistor constituting the switch circuit, a control signal inverted by an inverter is input to a gate of the p channel MOS transistor. Thus, both transistors are simultaneously turned on/off by those control signals. When an output voltage of the internal power supply circuit is monitored from the external terminal or when an internal circuit of a semiconductor integrated circuit is driven by a voltage applied to the external terminal, even if a potential of the external terminal overshoots to positive or negative values, the transmission of the potential to the internal circuit is cut off by the n channel MOS transistor or p channel MOS transistor. Therefore, in testing of monitoring of an operating state of the semiconductor integrated circuit and testing of an operating margin for an internal power supply voltage, no adverse influence is exerted on the internal circuit.
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