发明名称 Pipelined read architecture for memory
摘要 A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.
申请公布号 US5592435(A) 申请公布日期 1997.01.07
申请号 US19950575339 申请日期 1995.12.20
申请人 INTEL CORPORATION 发明人 MILLS, DUANE R.;SAMBANDAN, SACHIDANANDAN;KWONG, PHILLIP M. L.
分类号 G11C7/10;G11C7/22;G11C8/18;(IPC1-7):G11C8/00 主分类号 G11C7/10
代理机构 代理人
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