发明名称 |
Superscalar execution unit for sequential instruction pointer updates and segment limit checks |
摘要 |
An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.
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申请公布号 |
US5590351(A) |
申请公布日期 |
1996.12.31 |
申请号 |
US19940185488 |
申请日期 |
1994.01.21 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
SOWADSKY, ELLIOT A.;WIDIGEN, LARRY;PUZIOL, DAVID L.;VAN DYKE, KORBIN S. |
分类号 |
G06F9/32;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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