发明名称 Digital signal processing system for limiting a result to be predetermined bit count
摘要 A video codec (coder-decoder) system inputs consecutively admitted frames of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each block of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.
申请公布号 US5590291(A) 申请公布日期 1996.12.31
申请号 US19930000562 申请日期 1993.01.04
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 MURAKAMI, TOKUMICHI;OHIRA, HIDEO
分类号 H04N7/26;H04N7/36;H04N7/46;(IPC1-7):G06F3/14 主分类号 H04N7/26
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