Dynamic microbranching with programmable hold on condition, to programmable dynamic microbranching delay minimization

摘要

A pipelined, microcoded CPU employs conditional branching in microcode execution Data path conditions produced by one microinstruction are used in the selection of a following microinstruction. In high-performance systems, multiple cycle microbranch latency requires that the generation of microbranch conditions be pipelined. Usually a microbranch condition is used exactly once, at the earliest possible time, when dynamic microbranch conditions are only valid a fixed number of microinstructions later in the pipeline. Flexibility of the microcode algorithm is increased by selectively inhibiting the update of the dynamic conditions to delay the use of the condition by one or more cycles, under microcode control, thereby implementing dynamic microbranches, while allowing use of previous dynamic microbranch state.