| 摘要 |
Data terminal comprising a demodulator for a FSK phase-coherent modulated signal having at least two frequencies, comprising a PLL circuit (10) in which a phase detector is combined with a real-time integrator (15) and in which a sequencer (5) is included, so that the modulated signal is integrated around the zero crossings before a clock signal and digital data are extracted from this signal after a phase lock. As long as the PLL circuit (10) is in the unlocked state, the frequency with which the integrator (15) is driven by the sequencer (5) is equal to half the bit rate of the modulated signal while, for that matter, this frequency is equal to the bit rate.
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