| 摘要 |
A decimation filter includes a plurality of integration stages, at least one decimation stage, and a plurality of differentiation stages followed by a FIR filter. At least one of the integration stages, the decimation stage, and the differentiator stages, and the FIR filter are implemented in a single ALU which includes a single adder, a ROM, and a RAM. The different sampling rates of the integrator stage and the FIR filter requires the storage of intermediate results in RAM of the FIR filter calculations.
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