| 摘要 |
<p>I- and Q-channel signals are multiplied by spreading replica codes (24) and the products are integrated only for one spreading code period (25). Modulated data components and vestigial carrier frequency components are eliminated by subjecting the integrated signals (26) to amplitude square-law detection. The signal power of the sum of the signals (27) subjected to the amplitude square-law detection is found over one spreading code period (updating the clock phase of a digital control clock generator (30)) and each power information is stored in a memory circuit in an initial synchronous mode control circuit (29). The clock phase of the generator (30) is fixed with the phase of the spreading replica code at the maximum correlation detected power for one spreading code period. Thereafter, a spreading-code synchronized phase confirming mode is started. Since the spreading code synchronization confirming mode is provided in such a way, initial synchronization is established with a low synchronization error probability and a tracking mode is started in a short time.</p> |
