发明名称 |
Cyclic redundancy coder |
摘要 |
<p>A cyclic redundancy coder (10) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The cyclic redundancy coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a bit of a cyclic redundancy code word. A tap register (16) stores a tap position indicator indicative of tap positions in the cyclic redundancy code word that are subject to a logical operation. An input (18) provides input data to the cyclic redundancy coder. A logic feedback network (20-28) receives the data from the input and provides the logical operation. The logic feedback network also provides a plurality of data bits generated in response to the input data and each bit contained in each storage element identified by the tap position indicator. The cyclic redundancy code word is produced by applying at least one of the plurality of data bits to one storage element that is adjacent a tap position. <IMAGE></p> |
申请公布号 |
EP0750399(A2) |
申请公布日期 |
1996.12.27 |
申请号 |
EP19960109959 |
申请日期 |
1996.06.20 |
申请人 |
MOTOROLA LTD |
发明人 |
BENNETT, IRWIN;KING, BARRY;PAGE, ANDREW;GOLDING, PAUL |
分类号 |
G06F11/10;H03M13/09;H04L1/00;(IPC1-7):H03M13/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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