| 摘要 |
PURPOSE: To reduce the number of masks required for manufacturing an SRAM device. CONSTITUTION: An N-type polycrystalline silicon layer 40 which is simultaneously connected to both the gate electrode (polycide layer 27) of an N-type MOS transistor 14 and the diffusion area (N<-> -type impurity area 29 and N<+> -type impurity area 36) of an N-type MOS transistor 13 is newly provided. As a result, N-N contacts are formed between the layer 40 and the gate electrode of the transistor 14 and between the layer 40 and diffusion area of the transistor 13. On the other hand, the gate electrode (polycrystalline silicon layer 47) of a TFT 15 is formed in P-type and is only brought into contact with the polysilicon layer 40 at the bottom section of an opening 46 for contact. Since the gate electrode does not come into direct contact with the N-type diffusion area, such a case that a P-type impurity is diffused in the N-type diffusion area and increases the contact resistance of the diffusion area does not occur even when the gate electrode is formed in the P-type. While a P-N contact is formed between the gate electrode and the layer 40, the operation of the gate electrode is not hindered because the electrode is connected with the layer 40 in the forward direction. Therefore, the polycrystalline silicon layer 47 can be formed in a single conductivity (P type) and the manufacturing process of a semiconductor memory can be simplified by reducing the number of necessary masks. |
