| 摘要 |
PURPOSE: To obtain a frequency synthesizer utilizing DDS capable of outputting a high frequency signal while holding a synchronizing range with a wide PLL. CONSTITUTION: The frequency synthesizer is provided with a reference oscillation source 1 for applying a reference phase, a phase comparator 2 for comparing the phase of an output with the reference phase, a loop filter 3 for integrating the phase difference of the output to obtain DC voltage, an A/D converter 4 for converting the output into a digital signal, and a synthesizer DDS 5 for using frequency setting data applied with a generation frequency from the outside in terms of a phase increment value (Δϕ) and directly and digitally generating a signal with optional frequency less than 1/2 input clock frequency. The frequency of an output signal from the DDS5 is set up to the same frequency as that of the source 1 through a frequency divider 8 for frequency- dividing the output signal of the DDS5 into N components and the result is inputted to the phase comparator 2 to complete a phase locked loop PLL.
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