| 摘要 |
PURPOSE: To obtain a phase matching device having a short lock time and high system stability. CONSTITUTION: A delay/digital converter circuit 21 outputs time (tcycle-tcd) from the rise of an internal clock signal (a) up to the rise of a measurement end signal (b) to a digital/delay converter circuit 23 as digital delay time data D1. The circuit 23 outputs an output signal (b) obtained by delaying an external clock signal (e) by the delay time data D1 to a clock distribution circuit 24. The circuit 24 outputs a signal obtained by delaying the output signal (b) by (tcd) to respective circuit parts as an internal clock signal (a). Thereby the whole delay by the circuits 23, 24 becomes (tcycle). |
