| 摘要 |
<p>PURPOSE: To output a highly accurate frequency-divided clock from a reference clock by accumulating a set value outputted from a register in each reference clock and counting and outputting an overflow signal outputted at intervals of a prescribed time. CONSTITUTION: An accumulator 16 accumulates a set value outputted from a register 14 in each reference clock, i.e., executes cumulative addition or cumulative subtraction, and outputs an overflow signal, i.e., a carry signal in the case of cumulative addition or an inverse signal of a carry signal in the case of cumulative subtraction. A counter 18 counts, i.e., counts up or counts down the overflow signal outputted from the accumulator 16 and outputs a count signal of at least one bit. A selector 20 selects one bit in the count signal by a selection signal and outputs the selected bit as a frequency divided clock. Thereby the frequency of a reference clock can be divided by a frequency dividing ratio less than a decimal point by properly determining the number of bits in the accumulator 16 and the set value set up in the register 14.</p> |
