| 摘要 |
PURPOSE: To realize high speed set-up by connecting a scan path with a normal data path through a resistor means and connecting a latch, being used for both the scan path and the data path, to the data path side. CONSTITUTION: A latch connected with the I/O terminals of inverters 1, 2 is connected to node A of a data path having inverters 3, 4 operating with clocksϕ<-> ,ϕThe node A is connected through NMOS transistors 7, 8, operating as resistors, with node B of a scan path having inverters 5, 6 operating with clocksϕT<-> ,ϕT. The gates of transistors 7, 8 are connected, respectively, with the ground and power supply potential and the data path is isolated from the scan path by means of the ON resistance thereof. At the time of data transfer, load capacity for the latch decreases and a difference can be imparted to the rising characteristics between nodes A and B. Consequently, the node A can rise instantaneously and the data can be set up at high speed to the latch.
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