Bus synchronizing method and system based thereon

摘要

Bus clock generation circuits divide an output of an oscillation circuit with respect to frequency and output phase state signals. A synchronization circuit judges a setup condition on a second bus on the basis of the phase state signals and, when judging the satisfied setup condition, outputs a shift request signal to a CLK2 generation circuit. This causes the CLK2 generation circuit to change a phase of a clock CLK2 in such a manner that data transmission ends always within one period of the clock CLK2, thus a reducing synchronization overhead.