发明名称 |
Output buffer circuit for high-speed logic operation |
摘要 |
An output buffer circuit is provided, which enables to reduce the delay of a digital output signal with respect to an input digital signal. The output buffer circuit includes first and second FETs serially connected to each other. A gate of the first FET is applied with a first digital input signal. A gate of the second FET is applied with a second digital input signal. The first and second FETs operate to be opposite or complementary in logic state to each other. A digital output signal is taken out from a connection point of the first and second FETs. The circuit further includes a current source for causing a bias current having the same direction or polarity as that of a drain current of the first FET to flow through the first FET in the pseudo-OFF state. A turn-on speed of the first FET from the pseudo-OFF state to the ON state is enhanced by the bias current.
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申请公布号 |
US5587667(A) |
申请公布日期 |
1996.12.24 |
申请号 |
US19950575118 |
申请日期 |
1995.12.19 |
申请人 |
NEC CORPORATION |
发明人 |
INAMI, DAIJIRO;SATO, YUICHI |
分类号 |
H03K17/04;H03K17/687;H03K19/017;H03K19/0175;(IPC1-7):H03K19/017 |
主分类号 |
H03K17/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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