| 摘要 |
The circuit is provided for writing a field of the convergence correction data and using the correction data of the previous field in the next field, and includes a PLL generating the system clock, a horizontal address counter generating a horizontal address, a vertical address counter generating a vertical address, a field discriminator outputting the latch control signal discriminating between a odd field and a even field, a pulse generator outputting the switching control signal, a memory storing the average data calculated by CPU into a specific region and storing the convergence data into other regions, a A/D converter, a D/A converter, a low pass filter, a amplifier forcing a signal into a convergence yoke.
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