HIGH SPEED CYCLICAL REDUNDANCY CHECK SYSTEM USING A PROGRAMMABLE ARCHITECTURE

摘要

A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle. The system includes an input buffer, a latch, a CRC generator and write circuit, a status register, and an edit buffer which are connected on a common bus structure to provide maximum flexibility in performing error correction. The data flow may be programmed to bypass the CRC module if the data does not require error correction. Additionally, the raw data may be processed to accommodata different data protocols, so that the system is not restricted to a single data protocol.