Semiconductor memory having high speed and low power data read/write circuit.

摘要

Disclosed herein is a semiconductor memory, particularly a synchronous DRAM which includes a bus driving circuit driving read/write buses to first and second potentials in a write operation, a data amplifier driving the read/write buses to third and fourth potentials in a read operation, and a precharge control circuit precharging the data read/write buses to a precharge level for a predetermined level after the write operation has completed.