| 摘要 |
<p>The interface includes a control stage (1) connected in series with two inverting stages (2,3). The control stage receives input signals (i,e), delivered by a memory, and generates logic signals on two outputs (A,B). The inverted signals (E,F) are applied to a deviation reducing circuit (4) connected to an output stage (5). The deviation reducing circuit comprises a switching module connected between the output of the inverting stage (3) and a reference voltage (Vss). A second switching module is connected between the other output of the inverter and a supply voltage (Vcc). All the interface stages are built using NMOS and PMOS transistors.</p> |
