| 摘要 |
PURPOSE: To suppress the extension of delay for control signal generation by providing a specific input control means and a specific OR means and circulating only one pulse sent from a bistable element in the first stage and taking out the output of a preliminarily designated bistable element to generate a control signal. CONSTITUTION: Nine input control means AND gates 11 to 19 which are turned off at the time of input of a load pulse are inserted between stages of a 10-stage shift register where bistable elements (flip flops FF) are so connected that a bistable element FF1 in the first stage outputs '1' and bistable elements FF2 to FFn in second to tenth stages are simultaneously cleared to output '0' at the time of input of a reset signal. An OR means which operates OR between the load pulse and the output of the bistable element FF10 in the tenth stage is provided between the bistable element FF1 in the first stage and the bistable element FF10 . Only one pulse sent from the bistable element FF1 in the first stage is circulated by input of the reset signal or the output of the OR means, and the output of a preliminarily designated bistable element is taken out to generate the control signal. |
