发明名称 |
Semiconductor memory device permitting high speed data transfer and high density integration |
摘要 |
In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.
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申请公布号 |
US5586076(A) |
申请公布日期 |
1996.12.17 |
申请号 |
US19940304899 |
申请日期 |
1994.09.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MIYAMOTO, HIROSHI;MOROOKA, YOSHIKAZU;FURUTANI, KIYOHIRO;KIKUDA, SHIGERU |
分类号 |
G11C11/401;G11C7/10;G11C11/409;G11C11/4096;(IPC1-7):G11C7/00;G11C11/24 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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