| 摘要 |
<p>PURPOSE: To provide a variable delay circuit of less duty degradation by absorbing the output time differences of odd numbered inverting buffers by those of even numbered inverting buffers. CONSTITUTION: A variable delay circuit 1 is provided with inverting buffers 31 ,..., 3n in first to n-th stage ((n) is even) connected in series, switch circuits 51 ,..., 5n/2 connected to output terminals (b) of even numbered inverting buffers 32 , 34 ,..., 3n , and an up/down counter circuit 7 which selects one of these switch circuits 51 ,..., 5n/2 and outputs a signal from the selected switch circuit 11. The variable delay circuit 1 has load circuits 61 ,..., 6n/2 which are connected to output terminals (b) of odd numbered inverting buffers 31 , 33 ,..., 3n-1 and have loads equivalent to switch circuits 51 ,..., 5n/2 .</p> |
