发明名称 Power management for low power processors through the use of auto clock-throttling
摘要 A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.
申请公布号 US5586332(A) 申请公布日期 1996.12.17
申请号 US19930036343 申请日期 1993.03.24
申请人 INTEL CORPORATION 发明人 JAIN, SANJAY;AATRESH, DEEPAK J.
分类号 G06F1/32;(IPC1-7):G06F1/32 主分类号 G06F1/32
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