| 摘要 |
PURPOSE: To switch a clock signal source without giving effect on a clock output by providing a PLL circuit to the post stage of a changeover circuit. CONSTITUTION: A PLL circuit 9 is operated based on a reference signal inputted by a phase comparator 6. The phase comparator 6 outputs the phase difference between the reference signal and a feedback signal from a voltage controlled oscillator 8 as an error. A loop filter 7 eliminates a high frequency component included in the output of the phase comparator 6 and outputs only a DC component in the error signal. The voltage controlled oscillator 8 corrects its oscillating signal in matching with the output of the loop filter 7. The PLL circuit 9 matches the phase and the frequency of the feedback signal with those of the reference signal at an input section of the phase comparator 6 by repeating the operation above. Thus, the operation is continued without notifying the stop of a clock signal source 1 and changeover of clock signal sources 1, 2. |
