| 摘要 |
PURPOSE: To stably and surely fetch data from an asynchronous arithmetic circuit into a CPU. CONSTITUTION: A buffer 11 writes data d1 as they are, and data d3 inverted by an inverter 14 and a register 13 are written in a buffer 12. When the start of a read pulse R is positioned in the first half cycle of an arithmetic clock CL, on the other hand, the buffer 11 is read in accordance with the output of a gate 17 by a read pulse generating circuit composed of a D flip-flop 15, inverter 16 and gates 17 and 18 and when that start is positioned in the latter half cycle, the buffer 12 is read in accordance with the output of the gate 18. |
