发明名称 Multiple segmenting of main memory to streamline data paths in a computing system
摘要 Within a computing system, the main memory is segment in order to streamline data paths for data transactions between input/output devices (46,47). The computing system includes both a host bus (30) and an input/output bus (40). One or more processors (31,32) are connected to the host bus (30). A bus bridge (34) connects the input/output bus (40) to the host bus (30). The bus bridge (34) is used for transferring information between the host bus (30) and the input/output bus (40). The main memory for the computing system is segmented as follows. A first main memory segment (33) is connected to the host bus (30). A second main memory segment (43) is connected to the input/output bus (40). The first main memory segment (33) and the second main memory segment (43) are configured to appear to the processors as a single logical memory image. The segmented main memory is used to streamline data paths for the computing system. For example, a data transfer between a first input/output device (46) and a second input/output device (47) is controlled by the processor (31,32); however, during the first data transfer, the data itself is temporarily stored in the second main memory segment (43). This allows the data transfer to occur with only control information flowing through the bus bridge (34). The actual data is transported only on the input/output bus (40) between the second main memory segment (43) and the first input/output device (46), and between the second main memory segment (43) and the second input/output device (47). <IMAGE>
申请公布号 EP0747830(A1) 申请公布日期 1996.12.11
申请号 EP19960109092 申请日期 1996.06.05
申请人 HEWLETT-PACKARD COMPANY 发明人 EZZET, ALI
分类号 G06F15/16;G06F13/16;G06F13/36;G06F13/38;G06F13/40 主分类号 G06F15/16
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