| 摘要 |
An integrated device comprising isolating regions (18) of a first type of conductivity, each surrounding an epitaxial pocket (8) of an opposite type of conductivity, housing drain and source regions, and covered with an oxide layer (22a, 22b) housing gate regions (7) and over which extend the source (31), drain and gate connections. For linearizing potential distribution at the epitaxial pocket (8)- isolating region (18) junction and close to the source regions beneath the connections (31), these regions are provided with a double chain of condensers (11, 12) embedded in the oxide layer (22a, 22b) and the terminal elements (12a, 11a) and the intermediate element (11b) of which are biased to predetermined potentials (VG, ground, VD). <IMAGE> |
