发明名称 Computer graphics system having high performance primitive clipping preprocessing
摘要 A graphics processing circuit for use in a graphics accelerator that includes a clipping processor, with a vertex input data path (129) operatively connected to a vertex data input of the clipping processor. A clipping preprocessor (112) has a vertex data input operatively connected to the vertex input data path and a control output (109, 111) operatively connected to a control input of the clipping processor. The clipping preprocessor is constructed and arranged to perform an evaluation of a relationship between primitive vertex data from the vertex input data path and a clip region and to provide a signal on the control output based on this evaluation. <IMAGE>
申请公布号 EP0747861(A1) 申请公布日期 1996.12.11
申请号 EP19960107384 申请日期 1996.05.09
申请人 HEWLETT-PACKARD COMPANY 发明人 KOSS, LOUISE A.;NASH, MARY LOUISE
分类号 G09G5/00;G06T11/00;G06T15/30 主分类号 G09G5/00
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