| 摘要 |
The memory cell (10) includes a programmable antifuse (A1) which operates to place the memory cell (10) in a non-volatile state, e.g. logic '1', and also includes a pair of cross-coupled inverters (I1,I2). The antifuse is connected between an output (B) of one inverter and a ground node. Pref. there is a second antifuse (A2) connected between the inverter output (B) and a supply voltage (Vcc) and operates to place the memory cell in a second non-volatile state e.g. logic '0'. Only one antifuse is programmed in the cell. Each pair of cross-coupled inverters may include a p-channel transistor and an n-channel transistor, or a resistor and an n-channel transistor, connected in series between a supply voltage and the ground node. |
