发明名称 Real=time two=dimensional discrete cosine transform circuit
摘要 A rate dual ports buffer is provided for writing a set of N x N word data block at a first speed, after adjusting the data block, before delivering first one-dimensional data at a second speed. A selector has two input ports among which one port is coupled to the rate dual ports buffer for supplying the first one- dimensional data flow in the fist time period, and supplying the second one-dimensional data flow from another input port in a second time period. A one-dimensional DCT/IDCT operator is coupled to the selector for operating the one-dimensional data supplied from the selector. A row-column transpose buffer is coupled to the DCT/IDCT operator for transposing the first one-dimensional data after the DCT/IDCT operation and forming the second one-dimensional data to the selector. An inverse rate dual ports buffer coupled to the DCT/IDCT operator delivers the second one- dimensional data after the DCT/IDCT operation at the first speed.
申请公布号 NL1000506(C2) 申请公布日期 1996.12.10
申请号 NL19951000506 申请日期 1995.06.07
申请人 UNITED MICROELECTRONICS CORPORATION 发明人 PO-CHUAN HUANG
分类号 G06F17/14;(IPC1-7):G06T9/00;G06F17/16 主分类号 G06F17/14
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