Method and data processing system for determining electrical circuit path delays

摘要

A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162), and a set of logic value constraints are set for logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.