发明名称 |
Transistor structure for erasable and programmable semiconductor memory devices |
摘要 |
A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.
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申请公布号 |
US5583811(A) |
申请公布日期 |
1996.12.10 |
申请号 |
US19940275016 |
申请日期 |
1994.07.13 |
申请人 |
INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW |
发明人 |
VAN HOUDT, JAN;GROESENEKEN, GUIDO;MAES, HERMAN |
分类号 |
G11C16/04;H01L27/105;H01L27/115;H01L29/423;H01L29/788;(IPC1-7):G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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