| 摘要 |
An on-chip decoupling capacitor is disclosed. The capacitor of the present invention is fabricated using an embedded conductive layered structure. A first insulative layer, a first conductive layer, a second insulative layer, a second conductive layer, and a third insulative layer are deposited sequentially on a substrate having electronic circuitry. Next, a patterning layer is formed to provide for vias for interconnection between metal layers above and below the capacitor plates. An etch is then performed to form a via through the first, second and third insulative layers and the first and second conductive layers. Next, a fourth insulative layer is deposited and anisotropically etched to form sidewall insulators on the vias. Finally, interconnection between lower level metal levels and upper level metal levels is made through the vias. Additionally, methods of coupling the upper and lower capacitor plates to either power or ground are described.
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