发明名称 System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel
摘要 A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
申请公布号 US5583990(A) 申请公布日期 1996.12.10
申请号 US19930165266 申请日期 1993.12.10
申请人 CRAY RESEARCH, INC. 发明人 BIRRITTELLA, MARK S.;KESSLER, RICHARD E.;OBERLIN, STEVEN M.;PASSINT, RANDAL S.;THORSON, GREG
分类号 F16C39/06;F16C32/04;G06F15/16;G06F15/173;G06F15/80;H04L12/56;(IPC1-7):G06F13/00 主分类号 F16C39/06
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