| 摘要 |
1,204,593. Pulse shaping circuit. INTERNATIONAL BUSINESS MACHINES CORP. 2 Feb., 1968 [2 Feb., 1967], No. 5331/68. Heading H3T. A pulse thresholding circuit (more particularly for use in document scanning apparatus) operating on the leading or trailing edge of pulses having uniform edge widths such as are produced by scanning systems of finite aperture comprises a comparator to the inputs of which are applied the signal pulse and a delayed signal pulse, one input path including an attenuator and the delay being such that an attenuated leading edge terminates or a trailing edge starts during the corresponding edge of the unattenuated pulse. In Fig. 5 the comparator comprises transistors 40 to 43 having a common emittercurrent source 45. The inputs to the comparator comprise respectively a variable threshold voltage 28, an attenuated pulse I (Fig. 4), a pulse II with one unit delay and an attenuated pulse III with two units delay. Initially the emitter current flows to transistor 40. When the attenuated pulse I exceeds the threshold level the current diverts to transistor 41 but when the delayed pulse II exceeds this the current diverts to transistor 42 and thus to output inverter 52. It remains in this path until delayed pulse II at 42 decreases below the double delayed and attenuated pulse III at 43 whereupon the current is diverted from the output circuit to transistor 43. The rectangular pulses shown in the lower line of Fig. 4 are thus obtained. With 50% attenuation and 50% of the rise time as a delay unit the comparator changes over at the 50% amplitude points but other points can be obtained with other values and for non-linear edge slopes. The threshold input prevents operation by small amplitude pulses and a diode 33 limits the input pulse excursions. In Fig. 6 (not shown), the second delay and attenuator is omitted and the transistor (57) corresponding to 43 stores in an emitter capacitor (59) the peak amplitude of the attenuated signal applied to transistor 40 and this capacitor is coupled by a diode (58) to the common emitter circuit so that the output pulse terminates when the delayed input pulse falls below this level. In Fig. 7 current normally flows through diode 65, resistor 63 and transistor 62. A positive-going input pulse causes 61 to conduct and the voltage across a capacitor 66 follows the input pulse. This continues until the delayed pulse becomes of equal value whereupon the bases become of equal voltage and conduction in both transistors ceases. Capacitor 66 stores the attenuated peak value of the pulse and capacitor transistor 62 conducts again only when the delayed pulse falls below this value. |
