| 摘要 |
<p>A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.</p> |
