| 摘要 |
<p>An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder or the execution unit depending upon how much the present address must be incremented to obtain the new addresses.</p> |
