| 摘要 |
Output logic macrocells (504) for a programmable logic device as well as a block clock/control circuit (502) which allocates multiple clock signals (CK1-CKN) to each macrocell. Each macrocell includes a multiplexer (506) selectively providing one of the multiple clock signals to a clock input of a storage element (508), which operates similar to a latch. The storage element further receives a sum of product terms output from an OR gate at its data input. Vcc may be provided through the multiplexer to enable the storage element to function in a combinatorial mode. The multiple clock signals may include a clock signal provided to the multiplexer to enable the storage element to function in a latch mode. The clock signal may also be provided through a pulse generator in the block clock/control circuit to provide pulses having a pulse width delta to enable the storage element to function in a D-type flip-flop mode. For the D flip-flop mode, the storage element may be configured to operate as a P-type flip-flop so that its output will change states to follow its data input at a leading edge of its clock input, then does not change states for a period epsilon , wherein epsilon > delta , and then its output will change states to match its data input after the period epsilon if a signal received at the clock input has a period greater than epsilon . To provide reset or preset, a reset or preset signal may be provided at the data input of the storage element, as well as through a second pulse generator in the block clock/control circuit to the clock input of the storage element. The block clock/control circuit may be further configured to provide a dual edge clock mode, a mixed clock mode wherein two signals are provived on a single clock line, or other clocking modes.
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