| 摘要 |
PURPOSE: To provide the dynamic circuit which can suppress an increase in power consumption. CONSTITUTION: Between nodes N1 and N2 of a full-adder 1, NMOS transistors(TR) 2 and 3 are connected in series. A control signalϕo which is a pulse signal that goes up to an H level only for a certain time before a clock signal, the inverse ofϕfalls from an H level to an L level is inputted to the gate terminal of the NMO TR 2, and the TR turns on when the control signal pulse is at the H level. To the gate of the NMOIS TR 3, a sum signal So is inputted and the TR turns on when the sum signal So is at the H level. The nodes N1 and N2 are connected through both the TRs 2 and 3 which turn on and equalization is performed so that their voltages become as high as each other.
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