| 摘要 |
PURPOSE: To enhance the reading margin of a dynamic semiconductor memory by correcting the difference between cell write voltages required for reading out '0' and '1' thereby varying the readability of '0' read data and '1' read data. CONSTITUTION: A control clock ϕ0 is coupled through a capacitor C1 with a bit line-BL4 and a control clock ϕ1 is coupled through a capacitor C1 with a bit line BLA. Similarly, control clocks ϕ2, ϕ3 are coupled through capacitors C2 with bit lines-BLB, BLB and control clocks ϕ4, ϕ5 are coupled through capacitors C1 with bit lines-BLC, BLC. In such constitution, the capacitance of the capacitor C1 , C2 is differentiated from each other and the readability of '0' read data and '1' read data is varied thus enhancing the reading margin of a dynamic semiconductor memory. |
