| 摘要 |
PURPOSE: To obtain an NAND type mask ROM having gate length of half micron or less in which the ON current of memory cell transistor is increased without increasing the number of steps or masks. CONSTITUTION: Gate electrodes 6a-6e are formed through a gate oxide 5 on a P-type silicon substrate 1 partitioned through a field oxide 2 into a memory cell region 3 and a peripheral transistor region 4. Subsequently, N<-> type diffusion layers 7a-7g are, formed followed by deposition of an insulation film 8 by bias ECRCVD. Since the insulation film 8 is not deposited at the edge 12a-12h of a memory cell gate electrode, a side wall 9a, 9b is formed only in the peripheral transistor region 4 when etch back is effected on the entire surface. When an N<+> type diffusion layer 10a-10g is subsequently formed thereon, Nch single cell transistors 13a-13d and an Nch LDD transistor 11 are formed. |
