| 摘要 |
<p>PURPOSE: To generate a clock signal required for the operation of each circuit and to extend the degree of freedom of selection of a frequency of the clock signal by using number of externally mounted reference clock oscillators as small as possible in the digital modulation/demodulation circuit in which a circuit delaying and detecting digitally a reception signal, a clock recovery circuit detecting a symbol period of the reception signal based on the detection result, and a roll-off waveform generating circuit modulating transmission data are integrated into a 1-chip LSI. CONSTITUTION: A PLL circuit comprising a frequency divider 502, a VCO 504, an LPF 503 and a phase comparator 505 and a switch 501 are provided to generate a detection clock 306 for a detection circuit 301. Furthermore, a 2nd PLL circuit comprising a frequency divider 602, a VCO 604, an LPF 603 and a phase comparator 605 and a switch 601 are provided to generate a detection clock 403 for the clock recovery circuit 302 and the roll-off waveform generating circuit 401. A reference oscillator 702 in common to each of these circuits is provided to be an externally mounted oscillator for the LSI 201.</p> |
