发明名称 TEST PATTERN GENERATOR FOR LSI
摘要 PURPOSE: To perform a test efficiently in a short time using a small number of patterns. CONSTITUTION: A random test pattern generator 11 comprises a memory 13, a program counter control section 14, an execution circuit 15, and registers 16, 17. An algorithmic pattern generator 20 comprises an operating circuit 21, an initial value register 24, and an ALU variation value register 23. The algorithmic pattern generator 20 further comprises means for outputting the operation results from the operating circuit 21 based on a set pulse generated from the execution circuit 15 upon receiving a test pattern delivery instruction from the memory 13. A multiplexer 19 transfers a test pattern from the algorithmic pattern generator 20 to the register 16 while switching from a test pattern read out from the memory 13.
申请公布号 JPH08313602(A) 申请公布日期 1996.11.29
申请号 JP19960112646 申请日期 1996.05.07
申请人 TOSHIBA CORP 发明人 IZAWA KIYOSATO
分类号 G01R31/3183;G06F11/22 主分类号 G01R31/3183
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