OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM HIGH PULSE WIDTH

摘要

An open drain multi-source glitch free clock generator for use in a serial interface is disclosed. The clock generator includes logic circuitry for ANDing a first clock signal with a second clock signal to form an output clock signal. A low counter receives the first and second clock signals and upon a falling edge of the output clock signal, counts a low count for a period of time approximately equal to a longest logic low period of the first and second clock signals. A high counter receives the first and second clock signals and upon a rising edge of the output clock signal, counts a high count for a period of time approximately equal to a shortest logic high period of the first and second clock signals. The logic circuitry maintains the output clock signal at logic low until the low count expires and maintains the output clock signal at logic high at least until the high count expires. A method of generating an output clock signal is also disclosed.