| 摘要 |
<p>Memory requests are made to a cache memory and an external memory controller during the same clock cycle when the bus connected to the external memory is available. By making both memory requests during the same clock cycle rather than first accessing the cache memory as is conventionally done, the cycle time lost when the request is not stored in the cache memory can be eliminated. The unneeded external memory requests that result each time the request is stored in the cache memory are eliminated by gating the request to the external memory controller with a logic signal output by the cache memory that indicates whether the request is present.</p> |
