| 摘要 |
<p>A flash memory with a protocol which terminates a program load cycle, providing positive indication of the end of the load cycle. The memory includes an array (10) of floating gate storage elements, input/output circuitry (29) coupled to the array, and logic (18, 21, 37) for executing a process to store a block of data, including logic (37) to detect a last segment of the block of data in response to a pattern including at least one of addresses and data segments received at the input/output circuitry (29). The pattern may include consecutive matching addresses, both matching addresses and data segments, or a command address which is outside the address field of the memory. The flash memory includes a state machine (19) which automatically programs and verifies programming of the block of data after the last segment of the block is detected.</p> |
