| 摘要 |
<p>A partitioned decoder circuit (100) comprising a plurality of decoder circuit elements connected in series to receive a separate one of the asserted decoder enable signals (104). Each decoder circuit element includes a first clock input (CK) coupled to receive a precharge clock signal, an address input (D) coupled to receive address signal, address latching circuitry (106a, 106b, 106c and 106d) that latches the address signal in response to a polarity transition of the precharge clock signal and a second clock input. Significantly, gated discharge clock signal generation circuitry of each decoder element generates a gated discharge clock signal in response to the asserted decoder enable signal. The gated discharge clock signal is provided to the second clock input. A data output responds to the gated discharge clock signal being provided to the second input by providing an evalutation signal that corresponds to the latched address signal such that the result data signal includes the evaluation signal.</p> |
